Informatics Publishing Limited

C. Kumar Charlie Paul ¹, K. Megala Devi ¹, M. Hemapriya ¹, J. Felcia Jerline ²

Affiliations
1 Indus College of Engineering, IN
2 Dr. G.U. Pope College of Engineering, IN

Abstract

This paper presents a low power vlsi based noise removal and the experiments show, the proposed technique performs significantly better than standard median filter and achieves superior image quality. The intensity of impulse noise has the tendency of being either relatively high or relatively low. Thus, it could severely degrade the image quality and cause great loss of information details. So it is important to eliminate noise in the images before some subsequent processing. Image processing functions, like FIR filtering, pattern recognition or correlation, where the parallel implementation is supported by architecture matched special purpose arithmetic;high throughput FPGA circuits easily outperform even the most advanced DSP processors. Then Adaptive Median Filter solves the dual purpose of removing the impulse noise from the image and reducing distortion in the image. Adaptive Median Filtering can achieve the filtering operation of an image corrupted with impulse noise.

Keywords

FPGA, FIFO.

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C. Kumar Charlie Paul ¹, K. Megala Devi ¹, M. Hemapriya ¹, J. Felcia Jerline ²

Affiliations
1 Indus College of Engineering, IN
2 Dr. G.U. Pope College of Engineering, IN

Abstract

This paper introduces, a new intelligent hardware module suitable for the computation of an adaptive median filter is presented for the first time. The noise detection procedure can be controlled so that a range of pixel values is considered as impulse noise. In this way, the blurring of the image in process is avoided, and the integrity of edge and detail information is preserved. Experimental results with real images demonstrate the improved performance. The proposed digital hardware structure is capable to process gray-scale images of 8-bit resolution and is fully pipelined, whereas parallel processing is used in order to minimize computational time. In the presented design, a 3×3 or 5×5 pixel image neighborhood can be selected for the computation of the filter output. However, the system can be easily expanded to accommodate windows of larger sizes. The proposed digital structure was designed, compiled and simulated using the Modelsim and Synthesized in Xilinx.

Keywords

AMF, FPGA.

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J. Vinoth Kumar ¹, C. Kumar Charlie Paul ²

Affiliations
1 St. Peter’s University, Chennai - 600054, Tamil Nadu, IN
2 A. S. L. Pauls College of Engineering and Technology, Coimbatore - 641032, Tamil Nadu, IN

Abstract

The aim of the current research work is to design an efficient two-dimensional Discrete Wavelet Transformation (DWT) based image compression technique. In order to achieve best performance, Enhanced Half-Ripple Carry Adder (EHRCA) has been designed. Verilog Hardware Description Language (Verilog HDL) is used to model the EHRCA and DWT technique. DWT technique has been designed with the help of two types of filtering technique known as Low Pass Filter (LPF) and High Pass Filter (HPF). Three levels of decomposition is made by DWT process and each process have two levels compressions called “Row Wise Compression” and “Column Wise Compression”. In proposed DWT models, adders are recognized as high potential than other components. In order to improve the efficiency of DWT process, an efficient adder called “Enhanced Half-Ripple Carry Adder (EHRCA)” has been designed in this research work. Proposed EHRCA circuit offers 10.71% improvements in hardware slice utilization, 11.78% improvements in total power consumption than traditional Binary to Excess 1 Conversion (BEC) based Square Root Carry Select Adder (SQRT CSLA). Further proposed adder has been incorporated into Row Wise Compression and Column Wise Compression for improving the architectural performances of DWT. In future, proposed EHRCA based DWT will be useful in Discrete Cosine Transformation (DCT) and hybrid type and lifting based DWT techniques.

Keywords

Binary to Excess 1 Conversion based Carry Select Adder, Carry Select Adder, Hybrid and Lifting based Discrete Wavelet Transformation Technique, Row and Column Wise Compression, Very Large Scale Integration

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V. Mangaiyarkarasi ¹, C. Kumar Charlie Paul ²

Affiliations
1 St. Peter’s University, Chennai - 600054, Tamil Nadu, IN
2 A.S. L. Pauls College of Engineering and Technology, Coimbatore - 641032, Tamil Nadu, IN

Abstract

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

Keywords

Fast Fourier Transform (FFT), Multipath Delay Commutator (MDC), Orthogonal Frequency Division Multiplexing (OFDM), Split-Radix Fast Fourier Transform (SRFFT), Very Large Scale Integration (VLSI).

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